BEGIN:VCALENDAR
VERSION:2.0
PRODID:icalendar-ruby
CALSCALE:GREGORIAN
X-WR-CALNAME:IEEE SSCS Distinguished Lecture: The Road to Gate-All-Around C
 MOS 
X-WR-TIMEZONE:Pacific Time (US & Canada)
BEGIN:VEVENT
DTSTAMP:20260617T002406Z
UID:tag:localist.com\,2008:EventInstance_52632967263558
DTSTART:20260421T230000Z
DTEND:20260422T003000Z
DESCRIPTION:IEEE SSCS Distinguished Lecture\n\nThe Road to Gate-All-Around 
 CMOS Event Speaker\n\nAlvin Loke\, Senior Principal Engineer at Intel\n\nE
 vent Description\n\nDespite the much-debated end of Moore's Law\, CMOS sca
 ling still maintains economic relevance with 2nm gate-all-around SoCs (Int
 el 18A) already in high-volume manufacturing since January 2026. Area scal
 ing extensively driven by design/technology innovations co-optimized for p
 rimarily logic scaling continues to offer compelling node-to-node power\, 
 performance\, area\, and cost benefits. In this tutorial\, we will start w
 ith a walk through memory lane\, recounting a brief history of transistor 
 evolution to motivate the migration from the planar MOSFET to the fully de
 pleted FinFET. We will summarize the key process technology elements that 
 have enabled the finFET CMOS nodes\, highlighting the resulting technology
  characteristics and challenges. This will set the stage for transitioning
  to the nanoribbon gate-all-around device architecture and unveiling the m
 agic of how these devices are fabricated.\n\nSpeaker Biography\n\nAlvin Lo
 ke is a Senior Principal Engineer at Intel\, San Diego\, working on analog
  design/technology co-optimization for Intel’s gate-all-around CMOS. He 
 has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent\, AMD
 \, Qualcomm\, TSMC\, and NXP. Alvin received a BASc from the University of
  British Columbia\, and an MS and PhD from Stanford. After several years i
 n CMOS process integration\, he has since worked on analog/mixed-signal de
 sign\, focusing on a variety of wireline links\, including chiplet IOs\, d
 esign/model/technology interface\, and analog design methodologies. Alvin 
 has been an active IEEE Solid-State Circuits Society (SSCS) volunteer sinc
 e 2003\, having served as AdCom Member\, CICC Committee Member\, Webinar C
 hair\, Denver and San Diego Chapter Chair\, as well as JSSC\, SSCL\, and S
 olid-State Circuits Magazine Guest Editor. He currently serves as the VLSI
  Symposium Secretary\, SSCS Global Chapters Chair\, and again as SSCS Dist
 inguished Lecturer. Alvin frequently speaks on CMOS technology and its imp
 act on analog design\, having authored invited publications including the 
 CICC 2018 Best Paper and short courses at ISSCC\, VLSI Symposium\, CICC\, 
 and BCICTS.  His publications have received over 1900 citations to date.
GEO:44.567164;-123.278692
LOCATION:Kelley Engineering Center\, 1001
SUMMARY:IEEE SSCS Distinguished Lecture: The Road to Gate-All-Around CMOS 
URL;VALUE=URI:https://events.oregonstate.edu/event/ieee-sscs-distinguished-
 lecture-the-road-to-gate-all-around-cmos
CATEGORIES:Lecture or Presentation
CATEGORIES:Conference or Workshop
END:VEVENT
END:VCALENDAR