Characterizing On-Chip Traffic Patterns in Throughput Processors: A Deep Learning Approach

The machine learning and deep learning models have been very lightly explored in the area of analyzing the behavior of On-Chip network traffic. These models have proven their potential in the area of pattern recognition, classification etc... In this paper we analyze the spatial pattern that each workload exhibits in its life cycle during execution. We address the problems with current studies in analyzing workload behavior and provide a refined path with fewer variables to tackle while analyzing the behavior. We have identified the abstraction at which analyzing the traffic behavior will result in low loss of information and could still use image recognition like approach in solving On-Chip traffic pattern characterization.

Major Advisor: Dr. Lizhong Chen
Committee: Dr. Fuxin Li
Committee: Dr. Raffaele De Amicis
GCR: Dr. William H. Warnes