Real Time Self-Interference Cancellation For Wireless Transceivers

With the need for higher spectral efficiency and data rates the rise of simultaneous transmit-and-receive (STAR) radios is becoming increasingly valuable. While many systems employ two separate channels for transmit and receive to double the data speed, this comes at the cost of doubling the RF band. This same performance could be attained with a full duplex system with half the bandwidth. RF historically, has been incapable of full duplex due to the tremendous amount of self-interference (SI) on the receiver, but due to advances in both analog and digital cancelation, full duplex is realizable.

This project focuses on the digital back end of self-interference cancelation following the analog front end for full duplex applications implemented in hardware. Pairing software coefficient computation though cross-correlation, scaling optimization, and interpolation, with high speed FPGA processing to develop real time self-interference cancelation. Utilizing software configurable firmware on a Xilinx FPGA and a 16-bit ADC/DAC card at 1GSamp/sec to reduce the SI by more than 45dB.

Major Advisor: Arun Natarajan
Committee: Don Heer
Committee: Roger Traylor