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MS Final Exam – Pavan Kumar Ramakrishna

Energy-efficient OTA Architectures using Load-pole Cancellation

The CMOS two-stage OTA has been a key enabler for mixed-signal IC design for nearly four decades. This research focusses on a modified two-stage CMOS OTA that features load-pole cancellation (LPC); i.e., the resulting architecture is essentially a two-stage CMOS OTA with no load capacitance. The load-pole cancellation is achieved by adding an additional stage to the conventional Miller-compensated two-stage OTA. The compensation scheme is inherently Process-Voltage-Temperature (PVT) insensitive and a single-ended implementation achieves an 8x power improvement in a TSMC 180nm process. Design optimizations to maximize power savings for the LPC OTA are explored using a gm/id-based approach. Fully-differential class-AB architectures of the OTA are designed in a 180nm process that mitigate the slew-rate limitations seen in class-A versions of the LPC OTA. The OTA has been implemented in an amplifier, switched-capacitor filter and a low-dropout regulator.

Major Advisor: David J. Allstot
Committee: Tejasvi Anand
Committee: Gabor Temes
GCR: William Warnes

Thursday, February 28, 2019 at 2:00pm to 4:00pm

Kelley Engineering Center, 1005
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic


College of Engineering, Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

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