Ring Amplifier Optimized for High Resolution Analog-to-Digital Converter Applications

In recent years, SAR ADCs have been shown to achieve faster conversion times and improved power efficiencies due to their simple building blocks that are digital in nature and scale favorably with technology. High resolution ADCs with stringent noise requirement has led to the adoption of hybrid ADC architectures such as the two-step SAR. The two-step SAR ADC, also known as pipelined SAR ADC, combine the concepts of SAR and Pipeline ADC architecture where a residue amplifier provides a critical amplification step. An amplifier architecture well suited for residue amplification known as Ring Amplifier (RAMP) has enabled power efficient two-step SAR ADCs. However, RAMP based ADCs with greater than 14 bits of resolution has not been attempted in previous literature. In this work, the design and measurement of a high-resolution two-step SAR ADC utilizing an enhanced RAMP is demonstrated. Additional circuit techniques are introduced that contribute to the energy-efficiency of the ADC. The ADC implemented in 0.18um technology achieves a DR of 95dB and a Schreier FOM better than 180dB at both 2MS/s and 15MS/s.

Major Advisor: Un-Ku Moon
Committee: Gabor Temes
Committee: Arun Natarajan
Committee: Tejasvi Anand
GCR: Ravi Balasubramanian