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PhD Final Exam – Fawaz Alazemi

Routerless Network-on-chip

Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures. In this thesis, a new class of on-chip networks, referred to as Routerless (RL) NoCs, where routers are completely eliminated is explored. A novel design that utilizes on-chip wiring resources smartly to achieve comparable hop count and scalability to that of the router-based NoCs is proposed. Several effective techniques that significantly reduce the resource requirement to avoid new network abnormalities in routerless NoC designs are presented. Evaluation results show that, compared with a conventional mesh, the proposed routerless NoC achieves 9.5X reduction in power, 7.2X reduction in area, 2.5X reduction in zero-load packet latency, and 1.7X increase in throughput. In addition, compared with the state-of-the-art low-cost NoC design, the proposed approach achieves 7.7X reduction in power, 3.3X reduction in area, 1.3X reduction in zero-load packet latency, and 1.6X increase in throughput.  Moreover, the shrinking features sizes due to technology innovation results in increasing link failure rates. For RL NoC this is a major concern due to a large number of wires that RL NoC employs. To address a solution to this problem, a fault tolerance technique for permanent link failures without using redundant wires is introduced and this technique requires a minimal overhead to the existing RL NoC. The performance of the technique after a fault recovery is extensively assessed using synthetic traffic patterns and PARSEC workloads. On average, latency is increased by 5.2% and 5.8% for synthetic patterns and PARSEC workloads, respectively. Moreover, this technique requires only an additional 4% area and 25% of total power.

Co Advisor: Lizhong Chen
Co Advisor: Bella Bose
Committee: Ben Lee
Committee: Rakesh Bobba
GCR: William Warnes

Wednesday, June 12, 2019 at 10:00am to 12:00pm

Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic

Research

Organization
Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

calvin.hughes@oregonstate.edu

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