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PhD Final Exam – Hyunkyu Ouh

New Architectures and Circuits for Pushing the Dynamic Range and Multiplexing Boundaries of CMOS-Integrated Sensors

Over the last decades, CMOS-integrated sensors have made impressive progress in performance, form-factor, and energy-efficiency for various applications such as imaging, physical/chemical sensing, bio/health monitoring. In the era of the artificial intelligence (AI) and the internet-of-things (IoT), such CMOS-integrated sensors are essential for massive and comprehensive data acquisition, where sensing range (or dynamic range), signal fidelity (or signal-to-noise ratio), and data throughput are key factors. Towards pushing the boundaries of such sensing capabilities, in this dissertation, novel sensing architectures are presented with energy/area-efficient circuit design techniques for multi-channel CMOS optical sensors and neural interfaces. First topic is a fully-integrated, wide linear dynamic range optical sensor array combining linear and single-photon avalanche diode operation within each pixel. A pulse-counting readout scheme provides in-pixel digitization in an area-efficient manner for both operation modes, enabling fully parallel measurement across the array. The proposed dual-mode optical sensor array alternately requires high-voltage (10-20 V) and low-voltage supply (2-5 V) for reverse bias of the photodiodes, which is provided by a reconfigurable, closed-loop high-voltage charge pump in the same substrate. An 8 x 8 array architecture along with the dual-mode bias generator is fabricated in a general purpose 180 nm CMOS process and demonstrates 129 dB dynamic range while maintaining linear photoresponse operating with a dual-mode frame rate of 20 Hz. Second topic is a new approach for applying orthogonal code-division multiplex (CDM) encoding to current-mode and voltage-mode sensor arrays with analog-domain encoding directly in a single analog-front-end circuit, which enables simultaneous readout for multiple sensors. The approach is applied to a 8 x 16 array of CMOSintegrated photodetectors and implemented in a general purpose 180 nm CMOS process, where the 16 channel CDM-based oversampling readout achieves the SNR improvement of more than 12 dB compared with time-division multiplexing at the same sampling rate. In addition, a CDM-based neural recording architecture is presented, which offers a significant tolerance to interference that can be injected through long cables.

Major Advisor: Matthew L. Johnston
Committee: David Allstot
Committee: Un-Ku Moon
Committee: Tejasvi Anand
GCR: William H. Warnes

Friday, September 20, 2019 at 1:00pm to 3:00pm

Kelley Engineering Center, 1114
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic


Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

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