Active Noise Shaping Analog-to-Digital Data Converters
Analog-to-digital converters (ADCs) are widely used in many devices what we are using today. For bio-sensor devices, it requires high accuracy and low power. Therefore, high resolution and low power consumption within relative low bandwidth are desired for ADC design. In this work a medium-high resolution ADC is presented. Firstly, an 1st order active noise-shaping (NS) successive-approximation-register (SAR) ADC is presented. it uses two equal-valued capacitors as a digital-to-analog converter (DAC). The circuit provides first-order noise shaping, which can improve the ADC’s linearity. Due to the two-capacitor DAC, the design of reference and reference buffer is relaxed. The ADC was fabricated in 0.18 um CMOS technology. For a 2kHz bandwidth, it achieved a 78.8 dB SNDR and 87.6 dB SFDR. In addition, an improved version is presented. In this ADC, correlated double sample (CDS) is used to reduce the DC offset and 1/f noise from the OTA. Furthermore, correlated level shifting (CLS) helps to improve the gain of OTA. Besides, a digital calibration scheme is proposed to reduce the effect of parasitic and mismatch of the DAC. With the calibration, it gives a more than 13dB improvement on the SNDR. The proposed ADC was fabricated in 130nm CMOS technology. It achieved 85.1 dB DR, 82.6dB SNDR and 90.9dB SFDR with 32 OSR. It consumes 40uW power from 1.6V power supply.
Co Advisor: Un-Ku Moon
Co Advisor: Gabor Temes
Committee: Tejasvi Anand
Committee: Matthew Johnston
GCR: Yun-Shik Lee
Tuesday, December 3, 2019 at 9:00am to 11:00am
Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331
Calvin Hughes
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