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PhD Final Exam – Pedram Payandehnia

Power Efficient Architectures for Low Noise Switched-Capacitor Filters and High Accuracy Analog-to-Digital Converters

Filters and data converters are key analog-and-mixed-signal (AMS) building blocks in communication systems, such as software-defined radios and internet-of-things. In this dissertation, novel switched-capacitor filters and analog-to-digital converter (ADC) circuit configurations have been explored which are power efficient and are digital scaling friendly. First, a novel switched-capacitor low-pass filter architecture is presented. In the proposed scheme, a feedback path is added to a charge-rotating real-pole filter to implement complex poles. The selectivity is enhanced, and the in-band loss is reduced compared with the real-pole filter. The output thermal noise level and the tuning range are both close to those of the real-pole filter. A fourth-order filter prototype was implemented in a 180-nm CMOS technology. The measured in-band loss is reduced by 3.3 dB compared with that of a real-pole filter. The sampling rate of the filter is programmable from 65 to 300 MS/s with a constant DC gain. The 3-dB cut-off frequency of the filter can be tuned from 0.490 to 13.3 MHz with over 100-dB maximum stop-band rejection. The measured in-band third-order output intercept point is 28.7 dBm, and the averaged spot noise is 6.54 nV/Hz. The filter consumes 4.3 mW from a 1.8 V supply. Next, an opamp-free noise shaping successive-approximation register (SAR) ADC is presented. Third-order noise shaping is achieved by implementing a second-order passive filter and a passive error feedback topology. In the proposed scheme, the SAR error signals (including quantization noise, comparator thermal noise, and DAC settling error) are subjected to third-order noise shaping. Therefore, the thermal noise specifications of the comparator can be relaxed. Also, since no active element is used, the proposed scheme achieves a higher power efficiency than earlier SAR ADCs. Finally, a novel 0-2 Multi Stage Noise Shaping (MASH) ADC is presented. The first stage is implemented using a 4-bit SAR ADC. The second stage uses a VCO-based quantizer (VCOQ). Unlike earlier VCOQs which provide first-order noise shaping, the proposed VCOQ achieves second-order noise filtering. To implement this noise shaping, the quantization noise of the VCOQ is extracted as a pulse-width-modulated (PWM) signal, and it is fed back to the VCO input using a charge pump circuit. Any error related to the charge pump circuitry will be first-order shaped at the output. Simulation results confirm the second-order noise shaping of the output of the ADC, and an excellent (14-bit SNDR) performance with oversampling ratio (OSR) of 16.

Major Advisor: Gabor Temes
Committee Un-Ku Moon
Committee: Matthew Johnston
Committee: Arun Natarajan
GCR: Sharmodeep Bhattacharyya

Monday, November 19, 2018 at 12:00pm to 2:00pm

Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic


College of Engineering, Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

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