Design Considerations and Circuit Techniques for Robust Ring-Amplifiers

Ring amplifiers have shown excellent power efficiency in the latest state-of-the-art analog to digital converters (ADCs). This thesis describes circuit techniques to ensure robust operation of ring amplifiers using standard analog techniques and PID controller analogy. Large-signal and the small-signal analysis of a ring-amplifier are performed using simple RC settling and operational transconductance amplifier (OTA) based analysis. Design considerations and tradeoffs for speed, stability and noise are discussed in the context of SC amplifiers. Dead-zone regulation technique is discussed which employs replica biasing and current mirrors for PVT-tolerant biasing. Additionally, passive-compensation technique is discussed for improved large-signal response of ring-amplifiers. Implementation details for Pipeline ADCs using passively-compensated ring-amplifiers and correlated-level-shift (CLS) based ring-amplifiers are discussed. These ADCs are implemented in 65nm and 180nm CMOS process respectively. Finally, implementation details for a high PSRR LDO in 22nm FINFET process is discussed.

Major Advisor: Un-Ku Moon
Committee: Gabor Temes
Committee: Arun Natarajan
Committee: Raviv Raich
GCR: William Warnes