Design Techniques for Wide-bandwidth Continuous-time Delta-sigma Modulators with Noise-shaping Quantizers
Noise-shaping multibit quantizers in a ΔΣ modulator offer extra orders of noise shaping without increasing the loop-filter order and without compromising the stability of the modulator. This work presents two new architectures for improving the overall performance of continuous-time ΔΣ modulators using noise-shaped quantizers.
The first modulator architecture is motivated towards achieving high sampling frequencies using a VCO quantizer. The VCO based quantizer provides the benefits of first-order noise shaping, inherent DWA, and high sampling frequencies but suffers from a highly nonlinear voltage-to-frequency transfer characteristic which leads to performance degradation. In this work, a dual-path VCO quantizer nonlinearity cancellation technique is proposed that improves the overall modulator performance by cancelling the VCO quantizer non-linearity. The prototype modulator fabricated in a 65 nm CMOS technology achieves 76.1 dB DR, 73.5 dB SNDR and 88 dB SFDR over a 50 MHz signal bandwidth with an OSR of 15 and 51.8 mW of power.
The second modulator architecture, on the other hand, achieves 2nd order noise shaping from the quantizer itself, thus, reducing the needed loop-filter order by two and saving on active RC-OTA based integrator power. This new SAR-VCO based hybrid quantizer solves the VCO quantizer nonlinearity issue and also provides second order noise shaping. By using this SAR-VCO quantizer as an internal quantizer in a 2nd order ΔΣ loop, 4th order noise shaping is achieved using only two OTAs. The pipeline operation of the SAR quantizer and the VCO quantizer makes the delay of the hybrid quantizer equal to the delay of the SAR quantizer only. This reduces the excess-loop-delay introduced by the quantizer when used in a ΔΣ loop. Also, the quantization error leakage due to gain mismatch between the SAR path and the VCO path in the quantizer is noise shaped. The prototype modulator fabricated in a 65 nm CMOS process achieves 83 dB DR, 80 dB SNDR and 84 dB SFDR for a 12 MHz signal bandwidth with an OSR of 25 and 16.5 mW of power.
Co Advisor: Karti Mayaram
Co Advisor: Terri Fiez
Committee: Gabor Temes
Committee: Arun Natarajan
GCR: Sharmodeep Bhattacharyya
Tuesday, November 27, 2018 at 2:00pm to 4:00pm
Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331