Design of Energy-Efficient Equalization and Data Encoding/Decoding Techniques for Wireline Communication Systems
Ever increasing global internet data traffic has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals suffering from greater channel loss and exponential increase in power consumption, mainly caused by a heavier amount of required equalization. In this dissertation, two distinct methodologies for designing SerDes transceivers are presented: 1) a pulse width modulated (PWM) time-domain feed forward equalizer (FFE) and linearity improvement technique for higher-order pulse amplitude modulation (PAM) including PAM-8, and 2) an inter-symbol interference (ISI)-resilient data encoding and decoding technique with Dicode encoding and error correction logic for low-bandwidth wireline channels, as an alternative strategy for communicating in an energy-efficient way on bandwidth-limited wireline channels without using conventional equalizers or filters.
Major Advisor: Tejasvi Anand
Committee: Un-Ku Moon
Committee: Kartikeya Mayaram
Committee: Arun Natarajan
GCR: Hyun Seok Lee
Wednesday, June 17, 2020 at 1:00pm to 3:00pmVirtual Event