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PhD Final Thesis – Hossein Mirzaie

Digital solutions for analog shortcomings in delta-sigma analog-to-digital converters

Portable, high power efficiency communication devices is a growing market in the semiconductor industry. Analog-to-digital converters (ADC) are key interface that are used to digitize the sensed information. Recently, digital techniques have been proposed to improve analog building block power efficiency in sub-micron technologies. This research focuses on mixed signal approaches to improve the power efficiency of the noise shaping ADCs and mitigate analog inaccuracies such as non-linearity and mismatch. First, a novel continuous-time filtering delta-sigma ADC is proposed to save power and area. Digital techniques have been proposed to make the architecture more robust to out-of-band unwanted signals. A prototype was fabricated in a 65 nm CMOS technology achieving an SNDR of 72.4 dB operating at 250 MHz sampling frequency over 7 MHz bandwidth, with a power consumption of 16.3 mW. Next, A novel digital circuitry is proposed to improve the tolerance of a discrete-time delta sigma ADC to mismatch and enhance the resolution of an ADC in the presence of mismatch. A custom IC was fabricated in a 65 nm CMOS technology consuming 40.4 uA from a 1 V supply. It achieves 76.18 dB SNDR operating at 1.2 MHz sampling frequency and 25 kHz signal bandwidth.

Co Advisor: Kartikeya Mayaram
Co Advisor: Terri Fiez
Committee: Gabor Temes
Committee: Tejasvi Anand
GCR: Sharmodeep Bhattacharyya

Tuesday, November 13, 2018 at 2:15pm to 4:15pm

Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic


College of Engineering, Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

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