New Architectures and Circuits for CMOS Optical Detectors
My research focuses on novel architectures for CMOS optical detectors. First of all, I presented an approach for combining linear and single-photon avalanche diode operation in a single pixel to enhance low-light dynamic range of a photodetector array. Pulse frequency modulation and avalanche pulse counting provide in-pixel digitization for both operation modes, enabling full parallel measurement across the array. An 8 x 8 array architecture is fabricated in standard 180 nm CMOS and demonstrates 85 dB optical dynamic range and a maximum low-light frame rate of 130 Hz.
Secondly, I also presented a new approach for applying orthogonal code-division multiplex encoding to current-mode sensor arrays with analog-domain encoding directly in the column readout circuitry, which enables simultaneous readout for multiple sensors. The approach is applied to a 8 x 16 array of CMOS-integrated photodetectors and implemented in a general purpose 180 nm CMOS process. The sensor array demonstrates 63 dB SNR with an array-wide sampling rate of 100 Hz with 16-channel encoding, an improvement of more than 12 dB compared with time-division multiplexing at the same sampling rate. This work represents the first reported code-division multiplexed sensing architecture with analog-encoding front end, and the orthogonal coding scheme is broadly applicable to electronic current-mode sensor arrays for physical, chemical, and biological sensing applications without requiring sensor input encoding.
Major Advisor: Matthew Johnston
Committee: David Allstot
Committee: Un-Ku Moon
Committee: Arun Natarajan
GCR: William Warnes
Monday, November 5, 2018 at 2:00pm to 4:00pm
Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331