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PhD Preliminary Oral Exam – Lukang Shi

Two-Capacitor Noise-Shaping SAR A/D Converter

Analog-to-digital converters (ADCs) are widely used in many electronic devices. For bio-sensor devices, the ADC requires high accuracy and low power. In this research, a novel medium-high resolution and low power ADC is proposed. First, a 1st-order active noise-shaping successive-approximation-register (SAR) ADC is presented. it uses two equal-valued capacitors as a digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is 1, much smaller than in a conventional binary-weighted capacitor array, and hence the mismatch error can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity. Due to the two-capacitor DAC, the specifications of the reference and the reference buffer are relaxed. The ADC was fabricated in a 0.18 um CMOS technology. For a 2 kHz bandwidth, it achieved a 78.8 dB SNDR and a 87.6 dB SFDR. In addition, an improved version is presented. In this ADC, correlated double sample (CDS) is used to reduce the DC offset and 1/f noise from the OTA. Furthermore, correlated level shifting (CLS) helps to reduce effects of the finite gain of the OTA. With these two techniques, the design requirements of the OTA, which is used as an integrator, are relaxed. Also, a digital calibration scheme is proposed to reduce the effect of parasitic and mismatch effects of the DAC.

Co Advisor: Un-Ku Moon
Co Advisor: Gabor Temes
Committee: Tejasvi Anand
Committee: Matthew Johnston
GCR: Yun-Shik Lee

Wednesday, May 8, 2019 at 10:00am to 12:00pm

Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic


Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

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