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PhD Preliminary Oral Exam – Manjunath Kareppagoudr

Power Efficient Techniques for Switched Capacitor Circuits

Analog to Digital Converters (ADC’s) are the main building blocks of many IoT systems. These applications are battery operated and hence demand low power consumption. This work proposes (a) Design of 15-bit 20kHz bandwidth two-step incremental ADC with pseudo-pseudo differential(P2D) implementation which filters low-frequency noise and suppresses even harmonics with single-ended implementation and uses correlated level shifting (CLS) technique to further relax the OTA requirements used in the IADC. (b) the charge compensation technique to mitigate the slewing in switched capacitor circuits and hence save significant power consumption, the proposed technique is implemented in a single-bit second-order delta-sigma modulator with 25 kHz bandwidth.

Major Advisor: Gabor Temes
Committee: David Allstot
Committee: Un-Ku Moon
Committee: Matthew Johnston
GCR: William H. Warnes

Tuesday, December 17, 2019 at 9:00am to 11:00am

Kelley Engineering Center, 1005
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic


Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

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