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PhD Preliminary Oral Exam – Yongbin Gu

Architecture Optimization for Memory Systems of Throughput Processors

Throughput processors such as GPUs are widely used for accelerating compute- and data-intensive applications due to the extraordinary parallel computing capability. However, memory system designs can easily become a serious factor that prevents GPUs from achieving peak performance. In this research, we have proposed several architecture optimizations to improve the efficiency of memory systems in throughput processors: 1) we have proposed Cache Access Reordering Tree (CART), a novel architecture that can improve memory system efficiency by actively reordering memory accesses at L2 cache to be both cache-friendly and DRAM friendly; 2) we have developed Dynamically Linked MSHR (DL-MSHR), an effective approach that dynamically forms MSHR entries from a pool of available slots based on memory access patterns of different workloads; 3) we also designed a new memory management strategy for the Unified Virtual Memory (UVM) programming model. This strategy significantly improves the overall performance by up to 1.8X when applying the UVM programming model in GPUs.

Major Advisor: Lizhong Chen
Committee: Bella Bose
Committee: Ben Lee
Committee: Thinh Nguyen
GCR: Joseph Louis

 

Monday, March 2 at 3:00pm to 5:00pm

Kelley Engineering Center, 1007
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic

Research

Organization
Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

calvin.hughes@oregonstate.edu

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