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PhD Preliminary Oral Exam – Yunfan Li

Cost-Efficient Networks-on-Chip Design for Silicon Interposer-based Systems

Throughput-oriented many-core processors demand highly efficient network-on-chip (NoC) architecture for data transferring. Recent advent of silicon interposer, stacked memory and 2.5D integration have further increased data transfer rate. This greatly intensifies traffic bottleneck in the NoC but, at the same time, also brings a significant new opportunity in utilizing wiring resources in the interposer. In this paper, we propose a novel concept called Equivalent Injection Routers (EIRs) which, together with interposer links, transform the few-to-many traffic pattern to many-to-many pattern, thus fundamentally solving the bottleneck problem. We have developed EquiNox as a design example. We utilize $N$-Queen and Monte Carlo Tree Search (MCTS) methods to help select EIRs by considering comprehensively from topological, architectural and physical aspects. Evaluation results show that, compared with prior work, the proposed EquiNox is able to reduce execution t! ime by 23.5\%, energy consumption by 18.9\%, and EDP by 32.8\%, under similar hardware cost.

Major Advisor: Lizhong Chen
Committee: Bella Bose
Committee: Ben Lee
Committee: Thinh Nguyen
GCR: Yelda Turkan

Thursday, March 12 at 3:00pm to 5:00pm

Kelley Engineering Center, 1114
110 SW Park Terrace, Corvallis, OR 97331

Event Type

Lecture or Presentation

Event Topic

Research

Organization
Electrical Engineering and Computer Science
Contact Name

Calvin Hughes

Contact Email

calvin.hughes@oregonstate.edu

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